Analog Electronics I

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ivt" Semester [B.Tech.] ETEC-203 PaperCode: Time:I YzHrs.
FIRST-TERM E XAI\{INATION SePt.r2007 Sub: Analog Electronics-- I Max. Marks: 30
more' ancl Note: Attempt Q.No.l and any two more. ( r, n n .. * I o, r&lA* 0_o-.,,, fl.! n 0 density,electric field intensity, potentialin the e 1 (;) Draw and explain the variationof charge p-n depletionregionof a srepgraded junction (Na No) biasedwith a voltage,Vo. '-i of characteristic a p-n junction diode.
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R \tAa:10V, vi :0.2 sin 100nt, L = 2 KQ' Use Q 2 (a) In the circuit shown i n F i g . l , g i v e n : : lg9 for the large sig.ialmodel of the diode. Find the total voltage Vf : 0'6V and R1 (5) the across load,RL. (2) (b) Explain the termsIceo, Icpo. Shich is greater? (c)UFor the zener regulator shown in Fig.2, calculate the maximum and minimum zener (3) ,u/ dtodecurrent. Qw er, : Vz r $ o V '
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idealdiodes,find the values of labeledrzoltages shownin Fig.3, assuming Q.3 (a) For the circ';rit (5) and currents. AssumeFr : 100, (b) For the circuit shown in Fig.4, find the region of operation. (s) : : VBE,a"tine:0'7V, Vgg.sat 0.8V,VcE,sat 0.2V. 5V
& indicate in of e 4 (;) Draw the outputcharacteristics an npn transistor CB & CE configuration is Explain why the slopeof CE characteristics more. (5) the variousregionsof operation. Assumepp: 100, of of operatic'n the transistor. (tr)For the cirguit sirown,find the region (5) VCE,5.,:0.2V. VBE,ru,:0.8V, VBE.active:0.7V, lov
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EXAMINATION SECOND-TERM
[B.Tech'] IIIRD Semester Paper Code:ETEC-207 Time: I VzHrs. Note: AttemptQ.No.l and any two more' Not'., 2001 -Sub: Analog Electronics I Mar. Marks:30
(2)
Q.1(a)Explainthea.c.andd.c.loadlinesofaCEamplifier. Au andR"' of cE, cc and cB amplifiersin ternrsof Ai, Ri, ) comparethe performance values' Give aPProximate :1-h"l ( c ) S h o w t h a t h r c :- ( 1 + h r c ) ;h l . : h i . ; h . . tb': h''
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over fixed bias in terms of S(Ico)' (4) is self L''rcl\) srrq lrL'w Dvrr bias arrangement an improvement (a) Expilainhow e.2 rcV
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with RE, (ii) Darlington parr of (b) Draw and discuss important features (i) cE amplifier emitter follower for at high frequency.Derive an expression fp and Q.4 (a) Draw the hybrid nmodel find its reldtionship to parameterfr'
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: : h'" : 2X l}-a amplifier is sho*n in Fig.2. Given: hi. 1'1 KO; hf" l0; e.3 (a) A transistor A1 A/V. Determine: : IJI.I Avs: VoA/ri Ri & R:' and ho.:25X 10-6
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that desired Vce : 6.5V. (i) Determine Rs, (ii) S(Ico).
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response' (d)_Draw circuit of an Rc coupledamplifier & show its frequency the v Explainwhy the gain falls at low andhigh frequency.
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gain Au, and Ro for the two stageamplifiershown in Fig'3' ( (b) Find the voltage
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ExenalNATloN END'TERM DrcsrutunR-2001
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PaperCode:ETEC-207 PaperlD: 28207
Maximum Marks 75 (5) (5) ( 5) (5) ( 5)
Q1
(a (b )/ (c) (d)/ (e)
breakdown and comparethem' Define zenerbreakdown and avalanche an expressionfor potential narrier in a p-n junction diode- Derive Explain the formaiion of contactPotential. Wntiit'early effect?Explainbase width modulation' identifyA and B' toporigi"f i"i"".h of the four topologies feed back ampgtier List the fou.r a JFET' O"tiuu the relationbetweenVos and Vo of U N IT.I
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A b r i d g e r e c t i f i e r u s e s R l = 2 ' 4 k f ' ' e a c h d i o d e i sappried.e d t o h a v(a) peak dcn d R 'rmsr ' V r = 0 ' i d e a l i zcalculate e R t = 5 Q a and = c ot.?0v is vortagehavinguno A sinusoidar "r.pr'tuoe vottages(c)'ircoutput power (d) ac input power (e) (7) varuesof roadcurrent(b) dc "nd rms'output regulition' Derivenecessaryequation' and (0 percentage efficiency11 rectifications shown in fig'1, assuming that the for the circuit obtain the voltage transfer characlerist'[s = (5'5) and Rr O' Vi(t)= V sinrot and haveV, =O'OV diodesare identical
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si bar 2 Ann-type 1s anlopflg|a?^'':s:::||},*?#lLf[T;,Hi:1":Yf"n"o rever (b) verocitv (a) n"wsFind dopins and drift 8'MA ;:ffi: ii,; #;;;r
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capacitance.
ror an Derive expressionsdirrusions or a diode, (8)
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and explain' (3) for Drawthe Ebers-Moll transistor for equation a transistor. write the Ebers-Moll is improvedin a voltagedividerbias how stability Definettrreedifferentsiauiiitvfactors.Explain (s.5) circuit. OR (5) for pair and derivethe equatiotr input impedance' of Darlington Draw the circuit (7.5) Derivethe necessaryequations' DetermineAV and R, of tne cilruit uno*n in Fig.3.
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in shown fig.4' lco: 2mA F = 125' AVsandAV of the circuit A,Vr, Determine AVz,
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Sketch the small signal model for a common Drain FET and derive the equationfor voltage v
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are pt= 30, rd 5Ka. FinOtne voltagegain of the circuitshown in fig. B. FET parameters
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(4) of the of giving structure UJT.Explain working UJT. basic the Draw diagram source 150.Fortrigger of line has characteristics a straight _slo.pe Fora SCR,tne ga[e-caihode of gate powerdissipation 0.5W, computethe gate source voltageof 20V and allowable v (5'5) resistance ************
oR of Draw and explainV-l characteristics SCR'
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